1. Technical Field
The present invention relates to a multilayer wiring substrate and a method of manufacturing the same.
2. Related Art
In a multilayer wiring substrate in which wiring patterns are connected to each other via an insulating layer, an electrical connection between the respective wiring patterns is performed by a via that passes through the insulating layer. In such a multilayer wiring substrate. for example, JP-A-2004-356219 describes a multilayer wiring substrate shown in FIG. 10. In this multilayer wiring substrate, wiring patterns 102 are formed on one surface of a resin film 100, then resin layers 104 are formed between the respective wiring patterns 102. Concave portions 106 are formed through the resin layers 104 to expose the wiring patterns 102 by the laser beam, and then vias 108 are formed by filling a plating metal in the concave portions 106. Thus, the wiring pattern 102 is provided between the vias 108 facing each other.
JP-A-2004-311919 describes a via forming method as shown in FIGS. 11A to 11D. In this method, a through hole 202 shaped like a hand-drum is formed in an insulation substrate 200 (see FIG. 11A). Then, a thin film metal 204 is formed on the entire surface of the insulation substrate 200, including an inner wall surface of the through hole 202, by the electroless plating (see FIG. 11B).
Then, a plating metal layer 206 is formed by the electroplating using the thin film metal 204 as a power feeding layer (see FIG. 11C). At that time, electric charges are concentrated on a protruding portion that protrudes into the through hole 202, and thus the plating metal layer 206 is formed to cover the protruding portion of the through hole 202 such that the thickness of the plating metal layer 206 is larger than those of other portions.
Then, through the successive electroplating process, the protruding portions that protrude into the through hole 202 are connected to each other via the plating metal layer 206, as shown in FIG. 11D. Thus, the plating metal layer 206 is filled in the through hole 202, so that the via can be formed.
In the multilayer wiring substrate described in JP-A-2004-356219, the vias 108 can be formed relatively simply. The vias 108 are formed by filling the plating metal in the concave portions 106 from the exposed surfaces of the wiring patterns 102, and the plating metals filled in the concave portions 106 are connected to each other via the wiring pattern 102. In case where the plating metal filled in the concave portion 106 and the wiring pattern 102 are not suitably connected to each other, and further a tensile stress is given to the via 108 in the longitudinal direction, the plating metal filled in the concave portion 106 might be peeled off from the concave portion 106.
Meanwhile, in the via forming method described in JP-A-2004-311919, the via is formed by filling the plating metal in the through hole 202. Accordingly, a portion of the via is not peeled off from the through hole 202.
However, there is a problem in that it is difficult to form the through hole 202 in insulation substrate 200. In some cases, depending on the protruding portion that protrudes into the through hole 202, an opening of the through hole 202 might be blocked by the plating metal layer before the protruding portions are sufficiently connected to each other via the plating metal layer. Thus, voids may be generated in the via.